It is common in microprocessor-based electronic equipment to include two or more interconnected printed circuit boards, often including a main circuit board having a main controller or microprocessor (after termed the “motherboard” or “host”) and one or more connected daughtercards. In many electronic devices, some or all of the daughtercards may themselves be “intelligent”, i.e., may have their own programmable controllers.
For example, embedded systems which run complex operating systems and applications on a host/motherboard system often depend on intelligent daughtercards (cards controlled by a microprocessor, ASIC, or FPGA) to provide the functionality of a network interface.
One important system requirement is a host/daughtercard interface to transfer data between the host memory and the memory on board the daughtercard. Additionally, the host must be able to manage the memory of the daughtercard and also initialize and reconfigure the daughtercard in response to end user changes to the system.
Often, daughtercards, such as network interface cards or line cards, must be backward compatible to the host system and must use a low-bandwidth bus for both transferring packet data to be transferred to the network and control/configuration data.
For example, the host/daughtercard interface may be mechanically limited to a small number of pins and therefore must be used very efficiently to transfer data to a high speed network interface such as Gigabit Ethernet.
In particular, register updates on the daughtercard steal bandwidth required to transmit network data. A standard technique for updating register bits is a read-modify-write operation that requires three separate bus operations—read a register across host/daughtercard bus and store it's value in the host memory, modify stored context of the register by applying logical OR or AND operations, and write the modified value back to the register across the host/daughtercard bus. This approach also requires that all registers contexts be stored in the host memory. The stored copy may become “off-sync” with the real register values due to either software bugs or the faulty hardware controller design, which will result in the wrong system behavior.
Accordingly, improved and cost effective techniques for implementing daughtercard register updates without consuming excessive bandwidth on the host/daughtercard bus are required in many systems.